Exemplary embodiments of the present invention relate to a technology for reducing locking time of a Phase Locked Loop (PLL).
Technology of generating and using an internal clock is essential to a high-speed synchronous system. Mobile devices have been adopting the high-speed synchronous system as well. As a frequency of a system becomes higher, more power may be consumed in the system. Therefore, technology for reducing power consumption is needed in the system, especially in such mobile devices.
To reduce the amount of power consumption, physical methods such as decreasing parasitic components and lowering the level of power source voltage through micro-processing are used. Such physical methods, however, may require additional expenses. For this reason, a method of reducing power consumption within a system may be desirable. To reduce the power consumption within a system, a method of turning off a circuit which is not currently used inside the system or decreasing the operation frequency of the circuit is usually used. If it is possible to turn off a circuit or quickly change its frequency, power consumption can be reduced.
In particular, it may be desirable to reduce a locking time in a circuit like a phase locked loop, which generates an internal clock.
FIG. 1 is a block view illustrating a conventional phase locked loop.
Referring to FIG. 1, the phase locked loop includes a phase detector (PD) 110, a low pass filter 120, a controller 130, and an oscillator 140.
The phase detector 110 compares the phase of an input clock CLK_IN with the phase of a feedback clock CLK_FB and outputs the comparison result as an up signal UP and a down signal DN.
The low pass filter 120 filters noise from the up signal UP and the down signal DN.
The controller 130 generates oscillator control signals DCO_CONTROL_SIGNALS in response to noise-free up and down signals UP_F and DN_F outputted from the low pass filter 120. Depending on whether the noise-free up signal UP_F is enabled or the noise-free down signal DN_F is enabled, the controller 130 generates the oscillator control signals DCO_CONTROL_SIGNALS to increase or decrease the frequency of an output clock CLK_OUT generated in the oscillator 140.
The oscillator 140 generates the output clock CLK_OUT in response to the oscillator control signals DCO_CONTROL_SIGNALS. The frequency of the output dock CLK_OUT is determined based on the oscillator control signals DCO_CONTROL_SIGNALS. The oscillator 140 of this type is generally called a digital-controlled oscillator (DCO).
FIG. 1 illustrates an example where no circuits exist on the feedback loop, which is the current path for feeding back the output clock CLK_OUT as a feedback clock CLK_FB. A divider may be added to the feedback loop for the input dock CLK_IN and the output clock CLK_OUT, so that they may have different frequencies from each other.
The phase locked loop starts operating from the initial frequency of the output clock CLK_OUT, e.g., 300 Mhz, and operates in such a manner that it increases or decreases the frequency based on the phase comparison result produced in the phase detector 110. When the phase locked loop reaches a target frequency for the output clock CLK_OUT, it does not change the frequency of the output clock CLK_OUT anymore. When the frequency is no longer changed, the phase locked loop is said to be locked.
Herein, when the feedback loop does not include a divider as illustrated in FIG. 1, the target frequency of the output clock CLK_OUT is the same as the frequency of the input clock CLK_IN. When the feedback loop includes a divider, the target frequency of the output clock CLK_OUT becomes N times the frequency of the input clock CLK_IN, where N is a frequency division ratio of the divider.
FIGS. 2A and 2B are graphs showing a process of changing the frequency of the output clock CLK_OUT toward the target frequency according to the operation of the phase locked loop.
FIG. 2A shows a case where the target frequency of the output clock CLK_OUT is 300 Mhz. The frequency of the output clock CLK_OUT begins from the initial frequency value INI, which is 200 Mhz, and gradually increases according to the operations of the phase detector 110 and the controller 130. When the frequency of the output clock CLK_OUT reaches 300 Mhz, the phase locked loop is locked. In the case shown in FIG. 2A, since the predetermined initial frequency value INI of the output clock CLK_OUT and the target frequency of the output clock CLK_OUT have a relatively small difference of 100 Mhz, the locking time tLOCK may be relatively short.
FIG. 2B shows a case where the target frequency of the output clock CLK_OUT is 600 Mhz. The frequency of the output clock CLK_OUT begins from the initial frequency value INT, which is 200 Mhz, and gradually increases according to the operations of the phase detector 110 and the controller 130. When the frequency of the output clock CLK_OUT reaches 600 Mhz, the phase locked loop is locked. In the case shown in FIG. 28 since the predetermined initial frequency value INT of the output clock CLK_OUT and the target frequency of the output clock CLK_OUT have a relatively great difference of 400 Mhz, the locking time tLOCK may be relatively long.
The locking time of the conventional phase locked loop is changed according to the target frequency of an output clock. To be specific, as the difference between the target frequency and the initial frequency value of the output clock increases, the locking time becomes longer.
Since systems have been designed not to have a fixed operation frequency but to have varying diverse operation frequencies, the locking time of the phase locked loop may be a serious concern.